1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device on an N-type semiconductor substrate in which a power supply voltage of 30 V or higher is required, and to a method of manufacturing the semiconductor integrated circuit device.
2. Description of the Related Art
An electric circuit to be used for an electric apparatus is driven by an external power supply such as a battery. When a voltage value of the external power supply fluctuates, there is a fear of causing malfunction of the electric circuit or various abnormal phenomena. Accordingly, for a stable operation, a power management IC for regulating the external power supply to output a constant voltage and monitoring a fluctuation in voltage of the power supply is generally provided between the electric circuit and the external power supply.
One of requirements for the power management IC is high-voltage input and low-voltage output. In order to satisfy the requirement, a signal processing region for high voltage and a signal processing region for low voltage are required to be formed in a semiconductor integrated circuit device. Specifically, the signal processing region for low voltage using a low withstanding-voltage element is prepared for output circuits or internal logic circuits and the signal processing region for high voltage using a high withstanding-voltage element is prepared for input circuits or some output circuits. In this case, the circuit that requires the high withstanding voltage needs to have a large area so that an element region and an element isolation region have a structure resistive to a high voltage. Accordingly, the effort of suppressing cost rise of the semiconductor integrated circuit device becomes important in which the high withstanding-voltage element and the high withstanding-voltage structure are used only for a portion as small as possible and other regions are formed resistive only to a low voltage.
FIG. 6A is a schematic sectional view in a case where a low withstanding-voltage MOS transistor and a high withstanding-voltage MOS transistor are formed in the same semiconductor integrated circuit on a P-type semiconductor substrate.
A low withstanding-voltage NMOS transistor 501 formed on a surface of a P-type semiconductor substrate 1 includes a first gate insulating film 9, a gate electrode 6 formed directly on the first gate insulating film 9, and a drain region and a source region formed on both sides of the gate electrode 6. Each of the drain region and the source region includes an N-type high-concentration impurity region 17 having a low resistance to be brought into contact with a metal and a first N-type low-concentration impurity region 18.
On the other hand, a high withstanding-voltage NMOS transistor 503 includes the gate insulating film 9, the gate electrode 6 formed directly on the gate insulating film 9, and a drain region and a source region formed on both sides of the gate electrode 6. Each of the drain region and the source region includes the N-type high-concentration impurity region 17 and a second N-type low-concentration impurity region 19. An insulating film 13 having a thickness larger than that of the gate insulating film 9 is formed on each of the second N-type low-concentration impurity regions 19. The thick insulating film 13 is effective in electric field relaxation between a gate and the drain and therefore is beneficial.
The above-mentioned drain structure is adopted in a case where a drain withstanding voltage of 30 V or higher is required. The withstanding voltage is adjusted mainly by adjusting a length and a concentration of the second N-type low-concentration impurity region 19 on the drain side.
The N-type high-concentration impurity regions 17 of the high withstanding-voltage NMOS transistor 503 are generally manufactured in the same step as that of the N-type high-concentration impurity regions 17 of the low withstanding-voltage NMOS transistor for reducing process costs, and arsenic or antimony is used for the N-type high-concentration impurity regions 17.
Further, the second N-type low-concentration impurity regions 19 are often used as a channel-stop structure of a region outside the element so as to simplify the steps. Accordingly, the insulating film 13 formed in a LOCOS process is formed on the second N-type low-concentration impurity regions 19, and a concentration of the second N-type low-concentration impurity regions 19 is set to a concentration for preventing concentration inversion due to wirings. In general, when a frequency of use of the high withstanding-voltage NMOS transistor is low in the semiconductor integrated circuit, restrictions in terms of the structure for simplification described above are imposed on the high withstanding-voltage NMOS transistor, and therefore the element is designed under the restrictions described above.
Further, for the high withstanding-voltage NMOS transistor as illustrated in FIG. 6B, a third N-type low-concentration impurity region 14 having a depth as large as several micrometers is sometimes formed on the drain side of the high withstanding-voltage NMOS transistor so as to cover the entire N-type high-concentration impurity region 17 on the drain side and a part of the second N-type low-concentration impurity region 19 on the drain side. The formation of the third N-type low-concentration impurity region 14 has the effects of complementing for a small contact portion at a boundary between the N-type high-concentration impurity region 17 and the second N-type low-concentration impurity region 19 that are adjacent to each other so as to prevent breakdown due to heat generation caused by a high voltage and a large current that are to be applied during an electrical operation of the high withstanding-voltage NMOS transistor. Further, such a breakdown phenomenon affects not only instantaneous breakdown but also long-term reliability.
In addition, the third N-type low-concentration impurity region 14 on the drain side, which is a deep diffusion region, is also effective to improve resistance to electrostatic discharge (ESD) breakdown. The reason is as follows. Heat generation and temperature rise caused by an overcurrent at an ampere level due to instantaneously intruding static electricity can be reduced with a large contact area of a PN junction formed between the N-type diffused region having a large volume and the semiconductor substrate to suppress PN-junction breakdown (see, for example, Japanese Patent Application Laid-open No. 2008-010443).
As the semiconductor substrate to be used for the semiconductor integrated circuit described above, a P-type semiconductor substrate, which includes a large impurity concentration stable region in an ingot and provides a large wafer yield, is desired in economic terms. In functional terms and in view of users' requirements, however, an N-type semiconductor substrate is used frequently.
For example, in order to obtain a configuration in which a back bias is not applied so as to keep accuracy of the NMOS transistors to be integrated internally, there is employed a method of using the N-type semiconductor substrate, separating P-type well regions for respectively forming the NMOS transistors therein from each other, and arbitrarily changing a potential of each of the P-type well regions.
Hitherto, the integration of the high withstanding-voltage NMOS transistors on the N-type semiconductor substrate has the following problems.
First, the third N-type low-concentration impurity region 14 formed in the drain region of the high withstanding-voltage NMOS transistor in FIG. 6B is formed through a high-temperature long-time thermal treatment. Accordingly, in order to surround the entire region of the high-withstanding-voltage NMOS transistor as it is with the P-type well region, a P-type well diffusion thermal treatment step of more deeply forming the P-type well region than in the other related art is required. Accordingly, the thermal treatment should be carried out twice at a high temperature of 1100° C. or higher for a long period of time in order to form the deep well regions of both the regions. Consequently, a manufacturing time period is prolonged, while a required area is increased due to the expansion of diffusion in a transverse direction, resulting in inevitable price increase.
Further, there exists a method of employing a PN junction isolation using an epitaxial growth process or dielectric isolation using an SOI substrate, to thereby increase resistance of a double diffusion structure in a longitudinal direction to a high voltage. Although the increase in the required area can be suppressed by the above-mentioned method, manufacturing costs rise significantly. Thus, the price increase is still brought about with the above-mentioned method.
Further, as another method for the deep diffusion, a million electron volt (MeV) class ion implantation can be given. However, the MeV-class ion implantation requires an expensive apparatus. For products manufactured in an inexpensive process without employing a micro-process, in particular, product cost rise due to increase in apparatus costs cannot be ignored.
On the other hand, in a case where the resistance to the ESD or the like without forming the third N-type low-concentration impurity region 14 in the drain region of the high withstanding-voltage NMOS transistor 503, a resistor for noise reduction and the like are required to be provided. In order to prevent the breakdown due to heat generation, however, a large-size resistor that may affect the required area of the semiconductor integrated circuit device is required. Thus, the cost rise is still inevitable.